Electropolishing and electroplating methods

ABSTRACT

In one aspect of the present invention, an exemplary method is provided for electroplating a conductive film on a wafer. The method includes electroplating a metal film on a semiconductor structure having recessed regions and non-recessed regions within a first current density range before the metal layer is planar above recessed regions of a first density, and electroplating within a second current density range after the metal layer is planar above the recessed regions. The second current density range is greater than the first current density range. In one example, the method further includes electroplating in the second current density range until the metal layer is planar above recessed regions of a second density, the second density being greater than the first density, and electroplating within a third current density range thereafter.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application claims priority of earlier filed provisionalapplications U.S. Application Nos. 60/372,263, entitled “ENHANCINGSURFACE ROUGHNESS AFTER ELECTROPOLISHING,” filed on Apr. 12, 2002; No.60/382,133, entitled “METHOD FOR REDUCING RECESS IN COPPERELECTROPOLISHING,” filed on May 21, 2002; No. 60/387,826, entitled“METHOD TO PLATE PLANAR METAL FILM ON SEMICONDUCTOR WAFERS,” filed onJun. 8, 2002; No. 60/398,316, entitled “METHOD FOR REDUCING RECESSNON-UNIFORMITY ON PATTERNED TRENCH OR PAD AREA IN ELECTROPOLISHINGPROCESS,” filed on Jul. 24, 2002, all of which are incorporated hereinby reference in their entirety.

BACKGROUND OF THE INVENTION

1. Field

This invention relates generally to semiconductor processing methods,and more particularly to electropolishing and electroplating methods forelectropolishing and electroplating conductive layers on semiconductordevices.

2. Description of the Related Art

Semiconductor devices are manufactured or fabricated on semiconductorwafers using a number of different processing steps to create transistorand interconnection elements. To electrically connect transistorterminals associated with the semiconductor wafer, conductive (e.g.,metal) trenches, vias, and the like are formed in dielectric materialsas part of the semiconductor device. The trenches and vias coupleelectrical signals and power between transistors, internal circuit ofthe semiconductor devices, and circuits external to the semiconductordevice.

In forming the interconnection elements the semiconductor wafer mayundergo, for example, masking, etching, and deposition processes to formthe desired electronic circuitry of the semiconductor devices. Inparticular, multiple masking and etching steps can be performed to forma pattern of recessed areas in a dielectric layer on a semiconductorwafer that serve as trenches and vias for the interconnections. Adeposition process may then be performed to deposit a metal layer overthe semiconductor wafer thereby depositing metal both in the trenchesand vias and also on the non-recessed areas of the semiconductor wafer.To isolate the interconnections, such as patterned trenches and vias,the metal deposited on the non-recessed areas of the semiconductor waferis removed.

Conventional methods of removing the metal film deposited on thenon-recessed areas of the dielectric layer on the semiconductor waferinclude, for example, chemical mechanical polishing (CMP). CMP methodsare widely used in the semiconductor industry to polish and planarizethe metal layer within the trenches and vias with the non-recessed areasof the dielectric layer to form interconnection lines.

In a CMP process, a wafer assembly is positioned on a CMP pad located ona platen or web. The wafer assembly includes a substrate having one ormore layers and/or features, such as interconnection elements formed ina dielectric layer. A force is then applied to press the wafer assemblyagainst the CMP pad. The CMP pad and the substrate assembly are movedagainst and relative to one another while applying the force to polishand planarize the surface of the wafer. A polishing solution, oftenreferred to as polishing slurry, is dispensed on the CMP pad tofacilitate the polishing. The polishing slurry typically contains anabrasive and is chemically reactive to selectively remove from the waferthe unwanted material, for example, a metal layer, more rapidly thanother materials, for example, a dielectric material.

CMP methods, however, can have several deleterious effects on theunderlying semiconductor structure because of the relatively strongmechanical forces involved. For example, as interconnection geometriesmove to 0.13 microns and below, there can exist a large differencebetween the mechanical properties of the conductive materials, forexample copper and the low k films used in typical damascene processes.For instance, the Young Modulus of a low k dielectric film may begreater than 10 orders of magnitude lower than that of copper.Consequently, the relatively strong mechanical force applied on thedielectric films and copper in a CMP process, among other things, cancause stress related defects on the semiconductor structure that includedelamination, dishing, erosion, film lifting, scratching, or the like.

Another method for removing metal films deposited on the non-recessedareas of the dielectric layer includes electropolishing. However,because of the isotropic nature and poor planarization efficiency ofelectropolishing, the surface of the metal film topology is desirablyplanar to prevent recesses and the like that may degrade deviceperformance.

New processing techniques for depositing and removing metal layers aredesired. For example, a metal layer may be deposited or removed from awafer using an electroplating or electropolishing process. In general,in an electroplating or electropolishing process the portion of thewafer to be plated or polished is immersed within an electrolyte fluidsolution and an electric charge is then applied to the wafer. Theseconditions result in copper being deposited or removed from the waferdepending on the relative electrical charges.

BRIEF SUMMARY OF THE INVENTION

In one aspect of the present invention, an exemplary method is providedfor electroplating a conductive film on a wafer. One exemplary methodincludes electroplating a metal film on a semiconductor structure havingrecessed regions and non-recessed regions. The method includeselectroplating within a first current density range before the metallayer is planar above recessed regions of a first density. Further,electroplating within a second current density range after the metallayer is planar above the recessed regions, where the second currentdensity range is greater than the first current density range. In oneexample, the method further includes electroplating in the secondcurrent density range until the metal layer is planar above recessedregions of a second density, the second density being greater than thefirst density, and electroplating within a third current density rangethereafter.

The present invention is better understood upon consideration of thedetailed description below in conjunction with the accompanying drawingsand claims.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A and 1B illustrate cross-sectional views of interconnectstructures after metal plating and electropolishing respectively;

FIGS. 2A-2C illustrate cross-sectional views of a metal film profileduring an exemplary metal plating process;

FIG. 3 illustrates an exemplary relationship between hump size, levelerconcentration, and plating current;

FIG. 4 illustrates the relationship between plating current and humpsize with and without leveler;

FIGS. 5A-5C illustrate cross-sectional views of metal film profilesduring an exemplary metal plating process;

FIGS. 6A-6C illustrate cross-sectional views of metal film profilesduring an exemplary metal plating process;

FIGS. 7A-7C illustrate cross-sectional views of metal film profilesduring an exemplary metal plating process;

FIGS. 8A-8C illustrate cross-sectional views of metal film profilesduring an exemplary metal plating process;

FIG. 9 illustrates a cross-sectional view of an interconnect structurewith a dummy structure;

FIGS. 10A and 10B illustrate cross-sectional views of a metal filmprofile during an exemplary metal plating process;

FIGS. 11A and 11B illustrate cross-sectional views of a metal filmprofile during an exemplary metal plating process;

FIGS. 12A-12C illustrate cross-sectional views of a metal film profileduring an exemplary metal plating process;

FIGS. 13A-13H illustrate exemplary plating current sequences;

FIGS. 14A-14C illustrate plan views of various exemplary dummystructures;

FIGS. 15A-15C illustrate plan views of various exemplary dummystructures;

FIGS. 16A-16C illustrate plan views of various exemplary dummystructures;

FIGS. 17A-17C illustrate plan views of various exemplary dummystructures;

FIGS. 18A and 18B illustrate cross-sectional views of metal filmprofiles during exemplary metal plating processes;

FIGS. 19A-19F illustrate an exemplary electropolishing process for adual damascene structure;

FIGS. 20A-20D illustrate an exemplary electropolishing process for asemiconductor structure;

FIGS. 21A-21D illustrate exemplary metal layers of different grain sizesformed on semiconductor structures;

FIGS. 22A-22C illustrate various exemplary images of a copper layerhaving a relatively large grain size;

FIGS. 23A-23C illustrate various exemplary images of a copper layerhaving a relatively small grain size;

FIG. 24 illustrates a graph showing a relationship between grain sizeand surface roughness of a copper layer after electropolishing;

FIGS. 25A-25D illustrate a change in a metal layer grain size withrespect to time;

FIG. 26 illustrates a graph showing a general relationship of the metallayer grain size with respect to time;

FIG. 27 illustrates a graph showing the general relationship of thegrain growth rate with respect to the annealing temperature;

FIG. 28A illustrates an exemplary electropolishing apparatus;

FIG. 28B illustrates an exemplary process for electropolishing a wafer;

FIGS. 29A-29D illustrate an exemplary process for electropolishing aportion of a wafer;

FIGS. 30A-30D illustrate an exemplary process for electropolishing asemiconductor structure;

FIG. 30E illustrates an exemplary electropolished semiconductorstructure having copper recesses;

FIG. 31 illustrates an exemplary forward and reverse pulse waveform foran electropolishing method;

FIGS. 32A-32F illustrate an exemplary electropolishing process includinga forward and reverse pulse waveform; and

FIG. 32G illustrates an exemplary semiconductor structureelectropolished with a forward and reverse pulse waveform.

DETAILED DESCRIPTION

In order to provide a more thorough understanding of the presentinvention, the following description sets forth numerous specificdetails, such as specific materials, parameters, and the like. It shouldbe recognized, however, that the description is not intended as alimitation on the scope of the present invention, but is insteadprovided to enable a better description of the exemplary embodiments.

I. Method to Electroplate Planar Metal Films

According to one aspect, an exemplary method for plating planar metalfilms on semiconductor structures is described. The exemplary platingmethod includes plating a metal film with increased planarity overinterconnect structures formed on semiconductor wafers, for example,with reduced hump or over-plating and dishing. Various exemplary platingmethods are described for forming improved planar metal films onpatterned semiconductor structures by using combinations of chemistry,plating process sequences, and/or adding dummy structures withininterconnect structures.

The semiconductor industry generally uses copper in a damascene processto form metal interconnections in semiconductor devices. The damasceneprocess patterns dielectric material with recessed regions andnon-recessed regions as canal-like trenches and/or vias corresponding tothe desired interconnects. A barrier and seed layer may be deposited onthe dielectric material structure followed by copper plated on thebarrier and/or seed layer. Copper on the non-recessed regions istypically polished away by chemical mechanical polishing (CMP). CMPincludes both chemical (ion exchange) and mechanical (stress) processesto remove the copper layer on the non-recessed regions leaving copper inthe trenches and/or vias, i.e., the recessed regions. Pressure appliedon the polished surface may result in oxide loss, erosion, metaldelamination, and dielectric lifting.

In order to achieve significantly higher speed performance, copper isdesirably integrated with low-k dielectrics and preferably withultra-low-k dielectrics (k<2.5). The low-k dielectric implementationstrategy typically used today gradually migrates from oxide (k=4.0) tofluorinated oxide (k=3.5), and then to the low-k dielectrics withsuccessively lower k values of 3.0, 2.6, 2.2, and finally, k values ofless than 2.0. The multi-step low-k implementation strategy describedabove is very costly, carries high risk, and gives IC manufacturers agreat deal of uncertainty for the success of device manufacturability.Since each generation of low-k dielectric has its own mechanicalproperties and integration characteristics, IC manufacturers arerequired to develop new CMP and other related processes when migratingfrom one generation to the next. Tool and process extendibility,manufacturing yield, and device reliability have become major concernsin the industry because with each new manufacturing mode, ICmanufacturers must change low-k dielectric materials and processes.

An exemplary process that reduces the mechanical damage to low-kdielectric structures includes electropolishing. An exemplaryelectropolishing process is described in U.S. Pat. No. 6,395,152,entitled METHODS AND APPARATUS FOR ELECTROPOLISHING METALINTERCONNECTIONS ON SEMICONDUCTOR DEVICES, filed on Jul. 2, 1999, whichis incorporated in its entirety by reference herein. To improveelectropolishing processes, however, it is desired to increase theplanarity of the deposited metal film.

An exemplary profile of a copper film 104 plated by a conventionalplating process on a damascene structure is shown in FIG. 1A. Thesemiconductor structure includes a dielectric layer 108 formed over awafer 100 or previously formed semiconductor device structure. Thestructure may further include a barrier layer 106 and other materialsknown in the art. The structure includes a pattern of recessed regions101 r and non-recessed regions 101 n corresponding to trenches and/orvias separated by dielectric layer 108. Metal or copper layer 104 isformed over the structure filling the recessed regions 101 r and formedover the non-recessed regions 101 n. The underlying structure typicallyresults in a non-planar surface topology of copper layer 104 locatedover structures in dielectric layer 108. For example, the non-planartopology may include a hump 102 and recess 110 corresponding generallyto the underlying densely spaced recessed regions 101 r and wide openingrecessed regions respectively. Hump 102, recess 110, and othernon-planar features may be caused, for example, by the plating chemistryin an electroplating process.

FIG. 1B illustrates the structure of FIG. 1A after an electropolishingprocess. Metal layer 104 is typically polished back to the surface ofthe non-recessed areas such that metal layer 104 within the recessedregions 101 r, i.e., the trenches and vias, is isolated from adjacentrecessed regions 101 r. As shown in FIG. 1B, hump 102 may remain atleast partially over the dense pattern area and dishing, shown byrecessed region 110, may remain after electro-polishing due to theisotropic nature of the electropolishing. Humps and recesses may degradethe performance of the formed devices. For example, a hump left abovedensely spaced trenches or vias may cause an electrical short circuitbetween adjacent lines and recesses may result in the reduction of theconductance of the formed interconnection lines. Plating a planar metallayer 104 may reduce humps and recesses and improve device performance.

FIGS. 2A-2C illustrate an exemplary electroplating process over time forplating copper layer 204 over a dielectric layer 208 having a pluralityof densely spaced recessed regions 210 r and non-recessed regions 210 n.In general, a plating bath includes three main additives, e.g., anaccelerator, a suppressor, and a leveler. The primary function of theaccelerator is to enhance the plating process within recessed regions;the primary function of suppressor is to suppress the plating process onthe shoulder of the recessed regions; and the primary function ofleveler is to level the surface profile of the plated film, mostly tolevel hump 202. The combination of accelerator and suppressor results inthe super fill or bottom fill as illustrated in FIG. 2A. Moreparticularly, the plating rate at the bottom of the trench or recessedregion 210 r is significantly higher than at the top and shoulder of therecessed region 210 r. However, when trenches or vias are filled up, thechemicals in the trench region will continue to enhance the plating rateresulting in humps 202 as shown in FIG. 2B, which may run together overtime to form a larger hump 202 as shown in FIG. 2C.

FIG. 3 illustrates a relationship between leveler concentration andrelative hump height (often referred to as the “over-plating burden”) atincreasing plating currents 394, 392, and 390. The relationship suggeststhat hump size may be reduced with sufficient concentrations of levelerand increased plating currents as shown in the graph as levelerconcentration increases.

FIG. 4 further shows a relationship between the plating current and humpsize with leveler 498 and without leveler 496. As can be seen, theinstance with leveler 498 may reduce the hump size at most platingcurrents. However, at large plating currents a hump may still occurdespite leveler 498. Further, hump size is relatively greater at allcurrents without leveler.

FIGS. 5A-5C show the profiles of metal film 504 over time during anexemplary plating process at a relatively small plating current I₁. Theexemplary process includes directing electrolyte fluid at a rotatingchuck holding a wafer, but as will be recognized, other methods such asimmersion and the like may be used. The rotating chuck may rotate at aspeed in the range of, e.g., 50-200 rpm, and preferably 125 rpm. Aplanar metal film 504 can be plated under the following exemplaryprocess conditions:

Chemistry: Electrolyte Fluid Such as ViaForm Manufactured by Enthone-OMI

Accelerator: 1.5 to 2.5 ml/liter, preferably 2 ml/liter

Suppressor: 7 to 9 ml/liter preferably: 8 mi/liter

Leveler: 1.25 to 1.75 ml/liter, preferably: 1.5 ml/liter

Copper: 16 to 20 gram/liter, preferably, 17.5 gram/liter

Sulfuric Acid: 150 to 200 gram/liter, preferably 175 gram/liter

Rotation speed of wafer: 50 to 200 rpm, preferably 125 rpm

Current density: 0.5 to 5 mÅ/cm², preferably 2 mÅ/cm²

The exemplary process plates copper layer 504 over dielectric layer 508,filling the recessed regions 510 r and non-recessed regions 510 nrelatively quickly as seen at t₁. At a time t₂, where t₂ is greater thant₁, recessed regions 510 r are filled and metal layer 504 is relativelyplanar above the recessed and non-recessed regions 510 r and 510 n ofdielectric layer 508. At a time t₃, where t₃ is greater than t₂, theexemplary process continues to plate metal layer 504 at a constant rateabove recessed regions 510 r and non-recessed regions 510 n to create aplanar metal layer 504 of a desired height above the structure.

FIGS. 6A-6C show exemplary profiles of a metal film during a similarplating process, but at a relatively larger plating current than theprocess of FIGS. 5A-5C. The plating current density I₂ is in the rangeof 5 mÅ/cm² to 30 mÅ/cm², for example. The exemplary process at therelatively larger plating current produces humps 602 over recessedregions 610 r at t₂. The humps 602 may grow together to form a largerhump 602 at t₃.

FIGS. 7A-7C show exemplary profiles of a metal film profile duringanother exemplary metal plating process. As shown in FIGS. 7A and 7B,the plating process is conducted at a relatively smaller current I₁similar to FIGS. 5A-5C up to process time t₂ to produce a hump freeprofile of metal layer 704. The plating current may thereafter beincreased to I₂ and plated to time t₃, as illustrated in FIG. 7C, to adesired thickness of metal layer 704. The exemplary two-step platingprocess can achieve a planar metal film 704. In this exemplary process,the trenches or vias are fully plated to form a planar metal film 704before increasing the current to a level where humps will form. Forexample, if the trenches or vias are not fully plated when the currentis increased, a hump may appear above recessed region 7010 r as thecurrent is increased. FIGS. 8A-8C illustrate a metal film profile duringa metal plating process where the plating current is increased to I₂before the recessed regions 810 r are filled. As shown in FIG. 8B, thesmall hump 802 develops due to the large plating current I₂. As theprocess continues to plate copper film at large current I₂, the smallindividual humps grow into a large singular hump 802 as shown in FIG.8C. It should be recognized that the current from t₁ to t₂ need not beconstant and/or increase stepwise, but may increase smoothly during timet₁ to t₂.

Referring again to FIG. 1A a structure with high-density smalltrenches/vias and a large size trench and/or pad is shown. Due to therelatively large open area of recessed region 101 r shown to the right,which may include a trench and/or pad compared to the more narrow,densely spaced recessed regions 101 r shown to the left, the platingprofile may include dishing 110 as described above. In one exemplaryplating method, dummy structure 980 can be added inside the recessedregion 911 r, e.g., a trench and/or pad area, as shown in FIG. 9. Adetailed discussion of exemplary dummy structures may be found in U.S.patent application Ser. No. 10/108,614, entitled ELECTROPOLISHING METALLAYERS ON WAFERS HAVING TRENCHES OR VIAS WITH DUMMY STRUCTURES, filed onMar. 27, 2002, which is incorporated in its entirety by referenceherein.

FIGS. 10A and 10B show cross-sectional views of a plating profile duringan exemplary plating process at a constant current over time. In thisinstance, the plating process uses a relatively small current andleveler resulting in a flat profile above the relatively dense trench orvias 1010 r. The dummy structure area 1080, however, has more area to beplated resulting in a slight dishing 1020 of the final plating profile.The slight dishing 1020 will likely remain in the final profile after asubsequent electropolishing process as described above. Therefore, it isdesirable to have a process that can plate a planar film on both denselyspaced recessed regions 1010 r and the large trench area with dummystructure 1080. The size of dense trench or via region 1010 r can be inthe range of 0.035 to 0.5 micron with spacing between the trench orbetween the via in the range of 0.035 to 0.5 micron. The dummy structure1080 size may be in the range of 0.05 to 2.0 micron with space in therange of 0.05 to 2.0 micron, preferably 0.5 micron. Generally, the dummystructure should be designed with relatively small size and larger spaceto minimize the copper loss in the trenches.

FIGS. 11A and 11B show cross-sectional views of a plating profile duringan exemplary plating process including varying the current over time.The structure includes dummy structure 1180 formed at space w₁ and w₂,where w₁=w₂. Copper film 1104 is plated at a relatively lower platingcurrent I₁ until dense recessed regions 1110 r are filled as shown inFIG. 11A. Recesses 1120 are formed in the relatively wider trenches/padregions. The process continues to plate copper at a relatively higherplating current I₂, i.e., where I₂>I₁, and a hump will grow from dishing1120 such that the hump effect offsets the dishing to plate a planarsurface as shown in FIG. 11B. A hump does not form above the denserecessed regions 1110 r because the dense trenches or vias have alreadybeen filled during the first portion of the process by using therelatively small plating current I₁. The two-step plating processresults in a more planar profile of metal layer 1104 above the denselyspaced recessed regions 1110 r and the large trench and/or pad areahaving dummy structure 1180 formed therein.

FIGS. 18A and 18B show cross-sectional views of metal film profiles overexemplary dummy structures. The ratio of the depth H of a trench and/orpad to dummy structure space or width W between structures may be variedto increase the planarity of a metal film. In general, the ratio oftrench and/or pad height to dummy structure space is in the range of 0.3to 2.0, and preferably 1. A deep trench will have a tendency to havemore hump 1802 as shown in FIG. 18B, which will be used to balance thedishing 1810 for a wide space dummy structure, whereas a shallow trenchwill have a tendency to have less hump 1802 as shown in FIG. 18A.

FIGS. 12A-12C show cross-sectional views of a plating profile during anexemplary plating process that varies the current over time. Theinterconnect structure in dielectric layer 1208 is similar to that shownin FIGS. 11A and 11B, except that dummy structure 1280 is placed withinthe large trench or pad 1209, 1211 at space w₁ and space w₂, wherew₂>w₁. An exemplary three-step plating process is described to plate aplanar metal film 1204, e.g., that is hump-free and dishing-free, ondensely spaced recessed regions 1210 r and wide trench regions 1209 and1211 adjacent dummy structure 1280. The exemplary process through timest₁ and t₂ are similar to those previously described in FIGS. 11A and 11Bwith respect to increasing the current to create a planar topology abovenarrow recessed regions 1210 r and narrow space w₁.

At t₂, space w₂ still has dishing 1220 as shown in FIG. 12A. The currentis further increased to I₃ to plate above w₂. In particular, the processincreases the plating current from I₂ to I₃ to fill the recess 1220 andcontinues to plate the structure through t₃. Since the recessed region1210 r and 1209 have been previously filled with metal layer 1204 at t₁and t₂, the large current I₃ will not create a hump above these regions.The large plating current I₃ will create a hump above trench 1211because trench 1211 was not fully filled before the plating processincreases the current to I₃, as illustrated in FIG. 12B. I₃ may bevaried depending on the plating process, size of trench 1211, and thelike such that the hump created will sufficiently offset the dishing intrench 1211 formed during t₁ and t₂.

FIGS. 13A-13H show various exemplary plating current sequences over timethat may be used to achieve a planar metal layer. The exemplary platingcurrent sequences including both current level and timing may beadjusted according to the size, spacing, and density of trenches andvias as well as the size and space of a dummy structure. Generally, thecurrent sequence over time is controlled such that the effects of humpand dishing during plating balance or offset each other to create aplanar metal layer surface. The plating current can be linear as shownin FIG. 13A, non-linear, i.e., curved, as shown in FIGS. 13D-13H, or anycombination of linear and non-linear segments over time. Further, thecurrent sequences may decrease over periods of time as shown in FIGS.13G and 13H. In general, the plating current begins at a relativelysmall current and grows larger as the plating process progresses. Inaddition, the plating power supply can he run in constant voltage mode.In the present exemplary embodiment, the above description can changefrom current to voltage or to pulse power supply. A variety of pulsewaveforms may be used such as bipolar pulse, modified sine-wave,unipolar pulse, pulse reverse, pulse on pulse, and duplex pulse.Exemplary pulse wave forms are described in U.S. Pat. No. 6,395,152,entitled METHODS AND APPARATUS FOR ELECTROPOLISHING METALINTERCONNECTIONS ON SEMICONDUCTOR DEVICES, filed on Jul. 2, 1999, whichis incorporated in its entirety by reference herein.

FIGS. 14A-14C are plan views of various exemplary dummy structures.Dummy structure may include a metal plug 1420 placed outside the trench,or the pad area, often referred to as the open area or field area, asshown in FIG. 14A. Alternatively, dielectric slots 1430 can be placedinside the large trench and/or pad area 1404, or dielectric dots 1450can be placed inside the large trench and/or pad area 1404 as shown inFIGS. 14B and 14C.

FIGS. 15A-15C are plan views of additional exemplary dummy structuresthat may be included in relatively large vias or recessed regions. Metalplug dummy structure in FIG. 15A is similar to that illustrated in FIG.14A, except the metal plug column 1522 is shifted lower relatively tometal column 1520. Metal plug dummy structure in FIG. 15B is similar tothat shown in FIG. 15A, except metal plugs 1520 and 1522 are rotated 45degrees, which may reduce the inductance and capacitance of metal plug1520 and 1522. Dielectric dots 1550 that are placed inside the largetrench and/or pad area 1504 as shown in FIG. 15C are similar to thoseillustrated in FIG. 14C, except that dielectric dots 1550 are rotated 45degrees and individual columns are shifted lower relative to adjacentcolumn of dielectric dots 1550. The size and spacing may be adjusteddepending on the particular application and the like.

FIGS. 16A-16C are plan views of additional exemplary dummy structures.Metal plug dummy structure as shown in FIG. 16A is similar to thoseillustrated in FIG. 14A, except the metal plug column 1622 is shifted atan angle α. The angle α may be in the range of approximately 5 to 85degrees, and preferably about 25 degrees. Dielectric slots 1630 as shownin FIG. 16B are similar to those illustrated in FIG. 14B, except thatthe dielectric slots 1630 are disconnected from each other in order toenhance the conductance of copper trench and/or pad 1604. Dielectricdots 1650 placed inside the large trench and/or pad area 1604 as shownin FIG. 16B are similar to those illustrated in FIG. 14C, except thatdielectric dots 1650 are rotated 45 degrees. It should be recognizedthat the rotation angle of dielectric dots 1650 may be in the range of 0to 90 degrees, and further that dielectric dots 1650 may be shaped assquares, rectangles, circles, and the like.

FIG. 17A-17C are plan views of additional exemplary dummy structures.Metal plug dummy structures 1720 and 1722 as shown in FIG. 17A aresimilar to those illustrated in FIG. 14A, except the metal plug 1722 and1722 are rotated about 45 degrees. Metal plugs 1722 and 1722 may berotated between 0 and 90 degrees, and may be rotated at various degreeswithin a single structure. Dielectric slots 1730 as shown in FIG. 17Bare similar to those illustrated in FIG. 16B, except that the dielectricslots 1730 are disconnected at similar locations along the horizontaldirection. Dielectric dots 1750 placed inside the large trench and/orpad area 1704 as shown in FIG. 17C are similar to those illustrated inFIG. 14C, except that dielectric dots 1750 are shifted lower relative toadjacent columns of dielectric dots 1750.

Although exemplary plating processes have been described with respect tocertain embodiments, examples, and applications, it will be apparent tothose skilled in the art that various modifications and changes may bemade without departing from the invention. For example, variousdescribed methods may be used alone or in combination to electroplateplanar metal films.

II. Method for Reducing Recess in Electropolishing

According to another aspect, an exemplary method for reducing the recessin a metal trench or metal pad after an electropolishing process isdescribed. Using the methods and processes described herein, multi-layermetal interconnect structures may be fabricated with minimum recessand/or better planarity. In one example, a copper layer is formed over adielectric structure including recessed areas and non-recessed areas.The copper layer is planarized at a height above the non-recessedregions, for example, through a CMP process and/or an electropolishingprocess with dummy structures in the dielectric structure. Theplanarized copper layer is then electropolished to a height below thenon-recessed area height to form a recess. The non-recessed regions ofthe structure are then etched to planarize the copper layer with thenon-recessed regions or reduce the recess of the copper layer.

FIG. 19A illustrates an exemplary dual damascene structure after copperlayer 1902, or other suitable conductive layer, has been formed over thestructure. The dual damascene structure may be formed by any suitablemethod. For example, methods such as chemical vapor deposition (CVD),spin-on techniques, and the like may form the first dielectric layer1912. The thickness of dietetic layer 1912 can be in the range ofapproximately 1000 Å to 5000 Å, and preferably 3000 Å. An etch stoplayer 1910, such as silicon nitride or silicon carbide (SiC) layer isdeposited above the dielectric layer 1912. The thickness of etch stoplayer 1910 can be in the range of approximately 200 Å to 1000 Å, andpreferably 500 Å. In some examples, etch stop layer 1910 may be omittedand the etch timed to stop at the desired level to form the dualdamascene structure. A second dielectric layer 1908 is deposited on etchstop layer 1910 by using CVD or spin-on techniques, for example. Thethickness of second dielectric layer 1908 can be in the range ofapproximately 1000 Å to 4000 Å, and preferably 2000 Å. A hard mask layeror a second etch stop layer 1906 is deposited on the second dielectriclayer 1908. The hard mask layer or etch stop layer 1906 may be made ofsuitable materials such as SiO, SiC, SiN, and the like. The trench andvia may be formed by successive formations of photo masks and etches asis known in the art. For example, a first photo mask may be formed foretching the trench followed by a second photo mask to etch the via.

After etching trench and via, the barrier layer 1904 is deposited byCVD, physical vapor deposition (PVD), or atomic layer deposition. Thethickness of barrier layer 1904 can be in the range of 20 Å to 250 Å,depending on trench size and deposition techniques. Barrier layer 1904may include any suitable material, such as Tantalum (Ta), TaN, Titanium(Ti), TiN, TaSiN, Tungsten (W), WN, WSIN, and the like. After barrierlayer 1904 deposition, copper seed layer (not shown on drawing) can bedeposited on barrier layer 1904 by CVD, PVD, or ALD. Then copper layer1902 is deposited on copper seed layer, for example, by CVD, PVD,electroplating, electroless plating techniques, and the like.

As seen in FIG. 19A, copper layer 1902 may include recessed regions 1916r corresponding to the trench and via areas depending on the particulardeposition process. Planarity of copper layer 1902 may be increased bychemical mechanical polishing (CMP) a distance sufficient to remove therecess by including dummy structures within recesses of the dielectricstructure for hump free plating techniques and the like. Copper layer1902 is shown in FIG. 19B after a planarization process. An exemplaryplanarization method using a combination of CMP and electropolishing isdescribed in U.S. application Ser. No. 60/313,086, entitled METHODS TOPLANARIZE COPPER DAMASCENE STRUCTURE USING A COMBINATION OF CMP ANDELECTROPOLISHING, filed on Aug. 17, 2001, the entire content of which isincorporated herein by reference.

Copper layer 1902 is polished from non-recessed regions 1916 n by anelectropolishing method to isolate the copper from adjacent trenches andvias (not shown). In one exemplary process, copper layer 1902 ispolished to a height δh below the height of etch stop layer 1906 ornon-recessed regions 1916 n. The recess δh allows for a robustelectropolishing process and increases the probability that all copperon the non-recessed portions 1916 has been removed. The δh can be in therange of 100 Å to 1500 Å, preferably 500 Å. An exemplary process isdescribed, e.g., in PCT Application No. PCT/US99/15506, entitled METHODSAND APPARATUS FOR ELECTROPOLISHING METAL INTERCONNECTIONS ONSEMICONDUCTOR DEVICES, filed on Jul. 8, 1999, the entire content ofwhich is incorporated herein by reference. The recess of copper layer1902 will cause poor planarity when another dielectric layer, maskinglayer, or the like is deposited over the structure. For example, thepoor planarity can cause defocus of a lithography process, and the like.

To reduce the height of non-recessed regions 1916 r, barrier layer 1904and in some instances a portion of hard mask layer 1906 may be etchedaway by plasma etching, wet etching, or the like to form a planar topsurface of the structure as illustrated in FIG. 1D. In one example, aportion of the hard mask layer 1906 is etched such that the surfacelevel or height of copper layer 1902 is planar with the surface of theremaining portion of hard mask layer 1906.

Generally, it is desired that the polish of copper layer 1902 result ina δh less than the total thickness of barrier layer 1904 and thethickness of hard mask layer 1906. If δh is too great, the lowdielectric constant k of dielectric layer 1908 will be exposed whenbarrier layer 1902 is etched away from the nonrecessed regions 1916 r ofthe structure. This may lead to dielectric layer 1908 being etched, forexample, by a plasma etch. Generally, the plasma etch rate of the low kmaterial is higher than that of hard mask 1906 and copper layer 1902. Anetch may also damage or increase the k of dielectric layer 1908 ifdielectric layer 1908 is exposed.

After the etching process, a polymer layer (not shown) may be formed onthe surface of copper layer 1902 and hard mask layer 1906. Typically,the polymer layer is cleaned before additional layers are deposited. Thepolymer may be cleaned, for example, by a suitable plasma dry ashingprocess or chemical wet cleaning process.

A dielectric layer 1926 such as silicon nitride or SiC can be formed oncopper layer 1902 and hard mask layer 1906, as shown in FIG. 19E. Thethickness of dielectric layer 1926 can be in the range of 200 Å to 1000Å, and preferably 500 Å. Additionally, a passivation layer or the likemay be included over the structure.

As shown in FIG. 19F, the processes described in FIG. 19A may berepeated above dielectric layer 1926. Specifically, additional trenchesand vias may be formed with a dielectric layer 1920 and dielectric layer1924 formed on etch stop layers 1922 and 1926. Additionally, barrierlayer 1916 may be formed over the structure as well as a seed layer (notshown) and copper layer 1914. A similar process to FIGS. 19B-19E may beperformed to produce a planar structure.

FIGS. 20A-20D illustrate another exemplary method for reducing therecess in a metal trench or metal pad after an electropolishing process.In this instance the structure includes a dielectric layer 2012patterned with recessed regions 2016 r and non-recessed regions 2016 n.The non-recessed regions 2016 r further include a multi-layer hard masklayer including, for example, a lower hard mask layer 2006 and upperhard mask layer 2007. In one example, the upper hard mask layer 2007serves as a sacrificial layer to an etching process and the lower hardmask layer 2006 serves as an etch stop layer as described below. Hardmask layers 2007 and 2006 may be made of suitable materials such as SiO,SiC, SiN, and the like. A barrier/seed layer 2004 and metal layer 2002are deposited over the structure filling the recessed regions 2016 r.

Similar to FIGS. 19B and 19C, metal layer 2007 is planarized andelectropolished to a height δh below the height of non-recessed regions2016 n as shown in FIGS. 20B and 20C. Metal layer is preferably etchedto a height substantially planar with lower mask 2006. Barrier layer2004 and upper hard mask layer 2007 may be selectively etched away tolower mask hard layer 2006, where upper hard mask layer 2007 serves as asacrificial layer and lower hard mask layer 2006 serves as an etch stoplayer. For example, the materials of upper hard mask layer 2007 andlower hard mask layer 2006 may be selected such that a plasma etch orthe like removes upper hard mask layer 2007 and stops at lower hard masklayer 2006. The resulting surface of metal layer 2002 and lower hardmask layer 2006 are substantially parallel as illustrated in FIG. 20D.

Using the methods and processes described herein, multi-layer metale.g., copper, interconnect structure can be fabricated with minimumrecess and/or better planarity. Although the exemplary methods forreducing recesses in copper electropolishing have been described withrespect to certain embodiments, examples, and applications, it will beapparent to those skilled in the art that various modifications andchanges are contemplated. For example, various dielectric materials andprocessing techniques to planarize the copper layer, polish the metallayer and the like may be used.

III. Improving Surface Roughness

In an electropolishing process the surface of the metal layer may berough causing degradation of the performance of semiconductor devices.For instance, the surface of a copper layer after electropolishing canhave a surface roughness of up to a few hundred nanometers. Increasedsurface roughness may result in poor planarization, surface corrosion,yield loss, and the like. The grain size of a metal layer can becontrolled during various stages of exemplary plating and polishingprocesses to improve device performance and characteristics. Inparticular, during a plating process, additives such as brightener,leveler, and the like, can be used to control the grain size.Furthermore, the amount of time between the plating process and theelectropolishing process can be shortened to reduce the grain size. Inaddition, an annealing process can be used to increase grain size afterelectropolishing to improve electrical characteristics. Electropolishingmetal layers and metal interconnections on semiconductor devices isdescribed, e.g., in U.S. patent application Ser. No. 09/497,894,entitled METHODS AND APPARATUS FOR ELECTROPOLISHING METALINTERCONNECTIONS ON SEMICONDUCTOR DEVICES, filed on Feb. 4, 2000, whichis incorporated in its entirety by reference.

The amount of surface roughness after electropolishing can depend, atleast in part, on the microstructure of the metal layer beingelectropolished. In particular, FIGS. 21A-21D illustrate a semiconductorwafer 1000 after an electropolishing process and including metal layerswith different microstructures. The metal layers may also be formedwithin a trench or via of a semiconductor structure or the like.Typically, the size of the grains within the microstructure affect thesurface roughness of the metal layer after electropolishing because theremoval or polishing rate of the metal layer at the grain boundary andat the grain surfaces may differ. Furthermore, the polishing rate of themetal layer 2102 at different grain faces may differ. Accordingly, asillustrated in FIGS. 21A-21D and metal layers 2102, 2104, 2106, and2108, having increasingly larger grain sizes, the surface topographyafter electropolishing can vary based on the size of the grains in themetal layer. Generally, the smaller the grain sizes the lower thesurface roughness of the polished metal layer as seen in FIG. 21A.Similarly, the larger the grain size, the higher the surface roughnessof polished metal layer as seen in FIG. 21D.

FIGS. 22A-22C show images of a copper layer having a relatively largegrain size, e.g., a few microns. In particular, with reference to FIG.22A, a scanning electron microscope (SEM) image of the copper layersurface after electropolishing is shown. With reference to FIG. 22B, afocused ion beam (FIB) image of the same copper layer surface afterelectropolishing is shown from the same location as shown in FIG. 22A.The images shown in FIGS. 22A and 22B indicate that the surfaceroughness of the copper layer can have a pattern that matches thepattern of the grains in the copper layer. In addition, FIG. 22C showsan atomic force microscope (AFM) image of the copper layer surface afterelectropolishing. Based on this AFM image, the mean roughness (R_(a)) ofthe copper layer surface is 14 nm, and the max height (R_(max)) of thecopper layer surface is 113 nm.

In contrast to FIGS. 22A-22C, FIGS. 23A-23C show images of a copperlayer having a relatively small grain size, e.g., tens of nanometers. Inparticular, with reference to FIG. 23A, a scanning electron microscope(SEM) image of the copper layer surface before electropolishing isshown. With reference to FIG. 23B, a SEM image of the copper layersurface after electropolishing is shown. The images in FIGS. 23A and 23Bindicate that if a copper layer surface has a small grain size beforeelectropolishing, the copper layer surface may have a smooth surfaceafter electropolishing. In addition, FIG. 23C shows an atomic forcemicroscope (AFM) image of the copper layer surface afterelectropolishing. Based on this AFM image, the mean roughness (R_(a)) ofthe copper layer surface is 3.6 nm, and the max height (R_(max)) of thecopper layer surface is 30 nm.

FIG. 24 is a graph showing the relationship between grain size andsurface roughness of a copper layer surface after electropolishing forvarious chemicals included in an electrolyte fluid. Generally, thesurface roughness after electropolishing increases as the grain size ofthe metal layer increases. Thus, a smaller grain size leads to asmoother and more planar copper layer surface topology afterelectropolishing. Accordingly, controlling and reducing the grain sizemay reduce the surface roughness of the copper layer, improveplanarization, surface corrosion, and yield loss.

1. Using Additives to Control the Grain Size:

In one exemplary process for controlling or reducing the metal layergrain size additives may be included in the electrolyte fluid. Additivessuch as brightener, accelerator, suppressor, leveler, and the like, canbe used alone or in combination during the plating process to controlthe grain structure and enhance the gap filling capability of a metallayer on a semiconductor structure. In particular, additives such asbrightener, accelerator, leveler, and the like, can be added to aplating bath to control the grain size and grain structure. For example,a ViaForm plating bath, which is manufactured and commercially availablefrom Enthone-OMI, can be used to obtain a smaller grain size, e.g., asgrain size of less than a few hundred Angstroms. The ViaForm platingbath includes an accelerator, suppressor, and leveler. In particular,the accelerator has a concentration in the range of about 1.5 ml/literto about 2.5 ml/liter, and preferably about 2 ml/liter. The suppressorhas a concentration in the range of about 7 ml/liter to about 9ml/liter, and preferably about 8 ml/liter. The leveler has aconcentration in the range of about 1.25 ml/liter to about 1.75ml/liter, and preferably about 1.5 ml/liter. Although particularconcentrations of additives are described above, it should be noted thatthe concentrations of additives can vary depending on the application.Accordingly, the concentrations of additives can fall outside of theabove-described range depending on the particular application andprocess. The smaller grain size metal layer may then be electropolishedwith enhanced surface roughness.

2. Shortening the Time Between Plating and Electropolishing:

Another exemplary process for controlling or reducing metal layer grainsize includes reducing the time between a plating process and anelectropolishing process. Typically, after a plating process, the metallayer grain size increases over time. FIGS. 25A-25D illustrate thechange in a metal layer plated on a semiconductor wafer over a period oftime. With reference to FIG. 25A, after being plated onto wafer 2500,metal layer 2502 can have a microstructure with a small grain size onthe order of a few nanometers. Over time, with reference to FIG. 25B,the grains in metal layer 2502 can grow to a size on the order of tensof nanometers. With reference to FIG. 25C, the grains in metal layer2502 can continue to grow over time to a size on the order of hundredsof nanometers. Finally, with reference to FIG. 25D, the grains in metallayer 2502 can grow to a size on the order of a few microns.

FIG. 26 is a graph showing the general relationship between the timeafter plating and the metal layer grain size. Shortly after plating ametal layer onto a semiconductor wafer or structure, the metal layergrain size can increase slowly from point A to B, where the grain sizeat point A is less than 100 Angstroms and at point B is less than 1000Angstroms. Between points B and C, the metal layer grain size canincrease more rapidly, where the grain size at point C is less than10,000 Angstroms. Then, between points C and D, the metal layer canreach a saturated stage, in which the metal layer grain size generallyincreases more slowly if at all.

In one example, the time between plating and electropolishing the metallayer to form a metal layer with reduced grain size, is less than about20 hours, and preferably less than about 5 hours. The time is preferablysuch that the grain size of the metal layer does not reach the micron,and more preferably the sub-micron size or less.

3. Annealing After Electropolishing:

Another exemplary process for control of metal layer grain size includesheating or annealing the metal layer after an electropolishing process.A metal layer may be plated, electropolished, and then annealed afterthe electropolishing process. During annealing, the metal is heated fora period of time to allow grains within the microstructure of the metallayer to form new grains through a process typically calledrecrystallization. These new grains can have different and relativelylarger sizes from the grains in the microstructure before annealing thatmay increase the electrical characteristics of the metal. Further, inone example, the metal layer may be chemical mechanically polishedbefore the electropolishing process.

FIG. 27 is a graph showing the relationship between grain growth rateand annealing temperature for copper plated onto seed layers ofdifferent thickness. Note that FIG. 27 may depict the generalrelationship between grain size growth rate and annealing temperaturesfor other metals as well. Generally, the grain growth rate increases asthe annealing temperature increases and the thickness of the thin filmdecreases. A seed layer thickness of less than 1,500 Å may be used, andpreferably about 100 Å. Further, as the annealing temperature increases,the time for recrystallization of the copper microstructure decreases.

In one exemplary process to enhance surface smoothness, the metal layeris electropolished before annealing. More particularly, the processesbefore electropolishing can be chosen to form small grain sizes in themetal layer in order to reduce surface roughness and increase planarityafter electropolishing. The metal layer is then electropolished andthereafter the metal layer can be annealed using an appropriateannealing temperature, such as an annealing temperature between 100° C.and 300° C., and preferably 150° C., to form larger grain sizes withinthe metal layer. Alternatively, the metal layer may be annealed over asufficient time period. These larger grain sizes can improve theelectrical properties of the metal layer within vias, plugs, trenches,and the like, of the semiconductor device. Furthermore, if the metallayer is annealed after electropolishing, the surface of the metal layercan remain smooth, while the electrical properties of the metal layerare improved. The metal layer may be heated to annealing temperatures byany suitable method such as an infrared source with a rapid thermalprocess, an oven, and the like.

Although the exemplary methods for enhancing surface roughness have beendescribed with respect to certain embodiments, examples, andapplications, it will be apparent to those skilled in the art thatvarious modifications and changes are contemplated.

IV. Method for Reducing Non-Uniformity and Recess

According to one aspect, an exemplary method for reducing non-uniformityand recess in a metal trench or metal pad after an electropolishingprocess is described. The exemplary method includes applying analternating forward and reverse voltage pulse that may reduce thebuild-up of charge and improve copper recess uniformity and reduce thecurrent loading effect.

FIG. 28A illustrates an exemplary electropolishing apparatus, which hasbeen previously disclosed in U.S. Pat. No. 6,395,152, entitled METHODSAND APPARATUS FOR ELECTROPOLISHING METAL INTERCONNECTIONS ONSEMICONDUCTOR DEVICES, filed on Jul. 9, 1999, the entire content ofwhich is incorporated herein by reference, and in PCT Application No.PCT/US99/00964, entitled PLATING APPARATUS AND METHOD, filed on Jan. 15,1999, which is incorporated in its entirety by reference.

As shown in FIG. 28A, wafer 2802 can be rotated around its center axisand may also be translated in the x-axis direction such that electrolytefluid 2806 from nozzle 2810 can reach any location of the opposing majorsurface of wafer 2802. Nozzle 2810 can also be mobile and translatealong the x-axis independent of wafer 2802. The trajectory ofelectrolyte fluid 2806 on wafer 2802 may be a spiral curve or othersuitable trajectory to direct electrolyte fluid 2806 to desired portionsof wafer 2802. Power supply 2812 can operate at a constant current DC,pulse or RF mode or constant voltage DC, pulse or RF mode to provide apotential difference between metal film 2804 and a nozzle electrode 2808to electropolish a metal film or copper film 2804 on wafer 2802.

As shown in FIG. 28B, when metal film 2804 on the field of a die 2818including trenches and/or vias is removed, the copper films on the wafer2802 will not fully cover wafer 2802. As electrolyte fluid 2806 isdirected to different portions of wafer 2802, the copper area within thecolumn of electrolyte fluid 2806 will vary.

FIGS. 29A through 29D show the process of the stream of electrolytefluid 2906 approaching die 2918 in more detail. If the power supply isrunning at a constant current, the current density will be low in FIG.29A since the electrolyte column 2906 has not reached die 2918. Duringthis portion the current is passed primarily through a barrier layer orthe like formed on the wafer, which generally has a much lowerconductivity than the metal layer.

As shown in FIG. 29B, when electrolyte column 2906 reaches die 2918, thecurrent density in the portion of the stream of electrolyte fluid 2906over die 2918 increases to a high value. The current density increasesover die 2918 because copper is more conductive and easily polished thantypical barrier layer materials such as Ti, TiN, Ta, or TaN. As thestream of electrolyte fluid 2906 moves fully over die 2918 as shown inFIGS. 29C and 29D the polishing current density on die 2918 will reduceand reach a substantially constant value as the current is spread overthe full cross-sectional area of the stream of electrolyte fluid 2906.

FIGS. 30A-30D illustrate a cross-sectional view of the exemplaryprocess. As shown in FIG. 30A, negative charge (electron) 3080 is builtup on the interface between electrolyte fluid 3006 and barrier layer3005 because barrier layer 3005 is difficult to polish. When electrolytefluid 3006 is adjacent copper trench 3020, the negative charge 3080buildup on the surface of the electrolyte is discharged through trench3020 thereby increasing the polishing rate of trench 3020, as shown inFIG. 30B.

With reference to FIGS. 30C and 30D, as electrolyte fluid 3006 continuesto move over the second trench 3022, the negative surface charge 3080 isreduced further, causing the polishing rate on trench 3024 to be lowerthan that on trench 3022, and the polishing rate on trench 3022 is lowerthan that on trench 3020 and so on. Due to the changes in currentdensity, the polishing rate will also change accordingly. With referenceto FIG. 30E, because of the changes in polishing rate the copper recessof the first trench 3020 is larger than that of the second trench 3022,and the copper recess on the second trench 3022 is larger than that ofthe third trench 3024 and so on. The copper recess may cause conductancefluctuations of the copper line and degrade the performance of the finaldevice.

In one aspect, an exemplary electropolishing method is described usingpulse or alternating current voltages to minimize the polishing ratedifferences over trenches and reduce or prevent copper recess. In oneexample, the relationship of polishing rate uniformity on trenches,pulse frequency, and nozzle tangential moving speed are varied to reducecopper recess in an electropolishing method.

FIG. 31 shows an exemplary forward and reverse pulse waveform for anelectropolishing method. The waveform region of A to B is the forwardpulse, and waveform region of C to D is the reverse pulse. V₁ is theforward pulse voltage and V₂ is the reverse pulse voltage. t₀ is thepulse period, typically the time passed from A to E. The forward pulsewidth is t₁ and the reverse pulse width is t₂. The duty cycle inpercentage is t₁/t₀.

FIGS. 32A-FIG. 32F illustrate an exemplary electropolishing methodincluding the pulse waveform of FIG. 31. FIG. 32A shows electrolytefluid 3206 approaching trench 3220 and as the pulse waveform is at point“A,” and voltage V₁. As illustrated, the interface between electrolytefluid 3206 and the surface of the wafer is filled with negative charge3280.

FIG. 32B illustrates the electrolyte fluid 3206 that has moved adistance L₁ to a location adjacent trench 3220, and pulse waveform is atpoint “B.” At this edge the pulse waveform moves to point “C,” i.e. thereverse pulse region and voltage V₂. The electrolyte interface at pointC is charged by positive charge (ions) 3282, as shown in FIG. 32C. Inthis manner charge of electrolyte fluid 3206 is alternated at theinterface between the relatively high conductive metal or copper layerin trench 3220 and the relatively low conductivity barrier layer 3205.

As shown in FIG. 32D, as the electrolyte fluid 3206 moves a distance L₂across trench 3220 and pulse waveform moves to point “D,” V₂ prevents ahigh rate of polishing. When electrolyte fluid 3206 has moved partiallyover first copper trench 3220 the waveform moves to point to point “E,”and V₁ to polish copper in trench 3220. At this time, negative charge3280 is building up on the interface between electrolyte 3206 andbarrier layer 3205.

FIG. 32F shows that as the pulse waveform moves to point “F,” and thestream of electrolyte moves distance L₃, the negative charge 3280buildup on the interface of barrier and electrolyte will be dischargedon the copper in trench 3220, which may cause a higher polishing rate.The over polishing region width w, as shown in FIG. 32G, is proportionalto the forward pulse width and to the nozzle moving speed, i.e.,w=cVt₁   (1)Where c is constant, V is the tangential speed or velocity of nozzlerelative to wafer surface, and t₁ is the forward pulse width (see FIG.31).

Generally, a smaller w will reduce the recess depth d. In order toreduce w, a lower velocity V and a short forward pulse width t₁ arepreferred. In order to have a short forward pulse width, exemplarymethods may include either reducing the duty cycle (t₁/t₀) or increasingpulse frequency. For example, the duty cycle can be in the range of 20%to 80%, preferably 50%. The frequency can be in the range of 100 kHz to100 MHz, preferably 3 MHz. Velocity can be in the range of 100 mm/sec to2000 mm/sec, preferably 500 mm/sec.

For example, by substituting V=500 mm/sec, and duty cycle=50%, andt₁=0.2 E-6 second (2.5 MHz) into equation (1), thenw=c×500×0.2E-6=c×0.1×10⁻⁶ mm=c×0.1 micronWhere w is in the 0.1-micron magnitude range.

As previously disclosed in provisional application U.S. Ser. No.60/092,316, a variety of pulse or alternative current/power supplies canbe used in the exemplary methods, such as a RF power supply, trianglewave power supply, or any other type of power supply which can chargethe interface between electrolyte 1008 and barrier to positive andnegative side.

Although the exemplary method for reducing non-uniformity and reducingrecess has been described with respect to certain embodiments, examples,and applications, it will be apparent to those skilled in the art thatvarious modifications and changes may be made without departing from theinvention.

The above detailed description is provided to illustrate exemplaryembodiments and is not intended to be limiting. It will be apparent tothose skilled in the art that numerous modifications and variationswithin the scope of the present invention are possible. For example, thevarious processes may be used alone or in combination to improve devicemanufacturing and performance. Accordingly, the present invention isdefined by the appended claims and should not be limited by thedescription herein.

1. A method for electroplating a metal layer on a semiconductorstructure having recessed regions and non-recessed regions, comprising:electroplating within a first current density range before the metallayer is planar above recessed regions of a first density; andelectroplating within a second current density range after the metallayer is planar above the recessed regions, wherein the second currentrange is greater than the first current range.
 2. The method of claim 1,wherein the first current density range is between 0.5 mÅ/cm² and 5mÅ/cm², and the second current density range is between 5 mÅ/cm² and 30mÅ/cm².
 3. The method of claim 1, wherein electroplating within thefirst current density range is carried out at a constant currentdensity.
 4. The method of claim 1, wherein electroplating within thefirst current density range is carried out at an increasing currentdensity.
 5. The method of claim 4, wherein the first current densityincreases linearly.
 6. The method of claim 4, wherein the first currentdensity increases non-linearly.
 7. The method of claim 1, whereinelectroplating within the first current density range includesdecreasing the current density.
 8. The method of claim 1, whereinelectroplating within the second current density range is carried out ata constant current density.
 9. The method of claim 1, whereinelectroplating within the second current density range is carried out atan increasing current density.
 10. The method of claim 9, wherein thesecond current density increases non-linearly.
 11. The method of claim1, wherein electroplating within the second current density range iscarried out at a decreasing current density.
 12. The method of claim 1,wherein the recessed regions of a first density include recesses with asize between 0.035 to 0.5 microns and spacing in the range of 0.035 to0.5 microns, and a large recess with a dummy structure having a sizebetween 0.05 and 2.0 microns and spacing in the range 0.05 and 2.0microns.
 13. The method of claim 12, wherein the metal layer iselectroplated above the regions of the first density until the metallayer is planar above the regions of the first density, andelectroplating over a region of second density until the metal layer isplanar above the region of first density and the region of seconddensity, wherein the region of second density is greater than the regionof first density.
 14. The method of claim 13, wherein after the metallayer is planar above the region of second density and the region offirst density, electroplating at a third current density greater thanthe second current density.
 15. The method of claim 1, wherein the metallayer is electroplated with an electrolyte fluid including anaccelerator, suppressor, and leveler.
 16. The method of claim 15,wherein the accelerator concentration is between 1.5 and 2.5 ml/liter,the suppressor concentration is between 7 and 9 ml/liter, and theleveler concentration is between 1.25 and 1.75 ml/liter.
 17. The methodof claim 1, further including controlling the grain size of the metallayer with additives in the electrolyte fluid.
 18. The method of claim17, wherein the additives include at least one of a brightener,accelerator, suppressor, and leveler
 19. The method of claim 1, furtherincluding rotating the semiconductor structure with a chuck at arotation speed of 50-200 rpm.
 20. The method of claim 1, furtherincluding rotating the semiconductor structure with a chuck at arotation speed of 125 rpm. 21-78. (canceled)